Overcoming Design and Evaluation Challenges of Intra-Pair Skew in High-Speed Interfaces
Thursday, October 23, 2025, 12:30 PM - 1:00 PM

The amount of data processing is increasing due to the widespread use of AI and other high-bandwidth applications. Accordingly, the performance of high-speed digital interfaces used in computing, server, storage, and other data systems continues to evolve. Accordingly, the performance of high-speed digital interfaces, such as PCI Express, USB, DDR, and Ethernet used in such use cases continues to advance to keep pace.

As data rates increase, the unit intervals (UIs) become shorter and more susceptible to bit errors. For this reason, intra-pair skew is an important factor for engineers to consider when designing modern high-speed system. Existing methods to evaluate intra-pair skew  have limited capability or are not granular enough. New novel methods for measuring granular intra-pair skew are necessary to effectively verify interconnect designs for current and emerging use cases. 

This session will present the challenges associated with measuring intra-pair skew in today’s designs, as well as the limitations of traditional testing methodologies. A new approach featuring dual transmitters on a high-speed BERT for single-ended control of the phase of the signals within the differential pair will be presented. Sample measurements and results will be shown.